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SOC - Design Verification Engineer

役職名: SOC - Design Verification Engineer
勤務地: ホーチミン市
職種: 半導体
給与: VND 480,000,000 - 845,000,000 (Annual)
求人番号: PR/093199
担当者: Nguyen Thi Minh Trang (Kylie)
お問い合わせ先: minhtrang.nguyen@jac-recruitment.com
求人情報掲載日: 2024/02/05 12:45
COMPANY OVERVIEW
We are supporting our client who specializes in the Semiconductor industry focusing on SOC, Mega MCU.
JOB RESPONSIBILITIES
  • IP/SOC design verification
  • Review the IP/SOC specification and architecture
  • Extract the features and define the verification plan
  • Execute on the verification plan through testbench development, test generation, failure analysis, and coverage analysis/closure.
  • RTL and gate-level simulation
  • Design verification methodology and flow implementation and improvement
JOB REQUIREMENTS
  • 5+ years of experience in related work (SOC design verification)
  • Good understanding of computer architecture and Verilog
  • Understanding SOC design flow and methodology
  • Capability to extract the design features and define the verification plan
  • Failure analysis and decision-making
  • Project schedule management
BENEFITS
  • More details shall be discussed in the interview
Apply online or feel free to contact me directly for more information about this opportunity. Due to the high volume of applicants, we regret to inform that only shortlisted candidates will be notified. Thank you for your understanding.