Testability Design Engineer (DFT)

COMPANY OVERVIEW
We are supporting our client who specializes in the Semiconductor industry focusing on SOC, and Mega MCU.
JOB RESPONSIBILITIES

• Collaborate with cross-functional teams to define and develop design for testability (DFT) strategies for automotive silicon chips, including ADAS SoC, Mega MCU, and Gateway SoC.
• Design and implement RTL code, incorporating DFT structures, using DFT insertion tools, or using hardware description languages (HDL) such as Verilog or System Verilog.
• Develop and execute test plans and verification strategies to ensure designs meet DFT goals in automotive industry standards.
• Design and develop in-system test environments, including hardware and software components, to enable efficient testing and validation of RTL designs in the context of the target automotive system.
• Debug and resolve design and verification issues related to DFT especially in in-system test environments, working closely with other design and verification engineers to ensure the robustness and efficiency of RTL designs.
• Keep up to date with industry trends, best practices, and new technologies in automotive silicon chip design, with a focus on DFT and in-system test environments, and proactively contribute to continuous improvement initiatives.

JOB REQUIREMENTS

• 7 – 10 years of RTL design experience with Verilog or System Verilog
• English is  a must
• Familiar to IEEE1149/1500/1687 standards
• Experience with Tessentshell/Testkompress for ATPG
• Experience with Tessent MBIST and In-System Test
• Knowledge of PERL TCL or C/C++ is a plus

BENEFITS

• More details shall be discussed in the interview

Apply online or feel free to contact me directly for more information about this opportunity. Due to the high volume of applicants, we regret to inform that only shortlisted candidates will be notified. Thank you for your understanding.
 
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